The present invention relates generally to logic circuits and, more particularly, to half-rail logic circuits.
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1 shows a prior art half-rail differential logic circuit 100A and associated prior art control circuit 100B as was set forth in FIG. 1 of the 1997 IEEE International Solid-State Circuits Conference Paper ISSC97/SESSION 25/PROCESSORS AND LOGIC/PAPER 25.6 (hereinafter referred to as the ISSC97 PAPER 25.6). ISSC97 PAPER 25.6 is co-authored by the Inventor of the present invention and is incorporated herein, by reference, for all purposes.
As seen in FIG. 1 of the present invention, prior art half-rail differential logic circuit 100A included eight transistors, PFET 101, PFET 105, PFET 107, NFET 109, NFET 115, NFET 117, NFET 121, and NFET 125. Prior art half-rail differential logic circuit 100A also included differential logic 123 with inputs 151 and 153, output 111 and output 113.
As discussed below, prior art half-rail differential logic circuit 100A also required control circuit 100B. Control circuit 100B included six transistors: PFET 129; NFET 131; NFET 133; PFET 137; PFET 135 and NFET 139. Prior art control circuit 100B also included an enable out signal (eout) at terminal 143 and an enable out bar signal ({overscore (eout)}) at terminal 141. According to the prior art, the control signals eout and {overscore (eout)}, at terminals 143 and 141, respectively, were supplied to prior art half-rail differential logic circuit 100A as control signals ein and {overscore (ein)} as discussed below.
As discussed above, prior art half-rail differential logic circuit 100A required an enable in (ein) signal, coupled to the gate of NFET 121 and NFET 125, and an enable in bar signal ({overscore (ein)}), coupled to the gate of NFET 101. The control signals ein and {overscore (ein)} were supplied by prior art control circuit 100B from terminals 143 and 141, respectively. When multiple prior art half-rail differential logic circuits 100A were cascaded together, prior art control circuit 100B and control signals ein and {overscore (ein)} were necessitated to ensure that each prior art half-rail differential logic circuit 100A switched or xe2x80x9cfiredxe2x80x9d only after it had received an input from the previous stage.
Cascading is well known in the art. For a more detailed discussion of the cascading of prior art half-rail differential logic circuits 100A, and the operation of prior art half-rail differential logic circuit 100A and prior art control circuit 100B, the reader is referred to the ISSC97 PAPER 25.6 discussed above. A more detailed discussion of the operation of prior art half-rail differential logic circuit 100A and prior art control circuit 100B is omitted here to avoid detracting from the invention.
As noted above, when multiple prior art half-rail differential logic circuits 100A were cascaded together, each prior art half-rail differential logic circuit 100A required prior art control circuit 100B to ensure that each prior art half-rail differential logic circuit 100A switched or xe2x80x9cfiredxe2x80x9d only after it had received an input from the previous stage. However, prior art control circuit 100B was extremely complex, requiring at least six additional transistors and several circuit lines. Consequently, prior art half-rail differential logic circuit 100A required significant addition components and space. This, in turn, meant that prior art half-rail differential logic circuit 100A required more silicon, a more complex design and more components to potentially fail. In addition, prior art control circuit 100B not only added complexity to prior art half-rail differential logic circuits 100A, but it also loaded the output nodes 111 and 113 of prior art half-rail differential logic circuit 100A and drew current from output nodes 111 and 113 of prior art half-rail differential logic circuit 100A to charge the control signals ein and {overscore (ein)}. In addition, in the prior art, if prior art control circuit 100B were made small, the control signals ein and {overscore (ein)} were slow, and this slowed down the operation of prior art half-rail differential logic circuit 100A. Consequently, there was pressure to increase the size of prior art control circuit 100B. However, Increasing the size of prior art control circuit 100B to speed up the control signals ein and {overscore (ein)} also increased the loading on the output nodes 111 and 113 of prior art half-rail differential logic circuit 100A and therefore slowed down the evaluation of logic 123.
What is needed is a method and apparatus for creating half-rail differential logic that does not require the complex control circuitry of prior art half-rail differential logic circuits and is therefore simpler, more space efficient and is more reliable than prior art half-rail differential logic circuits.
According to the invention, the prior art control circuitry is eliminated. The clocked half-rail differential logic circuit of the invention is instead activated from a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit of the invention. Each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or xe2x80x9cfiredxe2x80x9d only after it has received an input from the previous clocked half-rail differential logic circuit.
According to the invention, clocked half-rail differential logic circuits do not require the significant additional components required in the prior art. This, in turn, means that the clocked half-rail differential logic circuits of the invention require less space, are simpler and have fewer components to potentially fail. In addition, clocked half-rail differential logic circuits of the invention eliminate the loading of the output nodes of the half-rail differential logic circuit since there are no control signals ein and {overscore (ein)}, and therefore no prior art control circuits to draw current from the output nodes to charge the control signals ein and {overscore (ein)}. Consequently, using the clocked half-rail differential logic circuits of the invention, speed is increased because there is less loading on the output nodes and the clocked half-rail differential logic circuit of the invention can start evaluating once a differential voltage develops between the complementary inputs coming from the previous clocked half-rail differential logic circuit.
In particular, one embodiment of the invention is a cascaded chain of clocked half-rail differential logic circuits. The chain includes a first clocked half-rail differential logic circuit. The first clocked half-rail differential logic circuit includes: a first clocked half-rail differential logic circuit clock input terminal; at least one first clocked half-rail differential logic circuit data input terminal; and at least one first clocked half-rail differential logic circuit data output terminal.
The cascaded chain also includes a second clocked half-rail differential logic circuit. The second clocked half-rail differential logic circuit includes: a second clocked half-rail differential logic circuit clock input terminal; at least one second clocked half-rail differential logic circuit data input terminal; and at least one second clocked half-rail differential logic circuit data output terminal.
According to the invention, the at least one first clocked half-rail differential logic circuit data output terminal is coupled to the at least one second clocked half-rail differential logic circuit data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first clocked half-rail differential logic circuit clock input terminal and a second clock signal is coupled to the second clocked half-rail differential logic circuit clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked half-rail differential logic circuit clock input terminal and the second clocked half-rail differential logic circuit clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked half-rail differential logic circuit that includes a clocked half-rail differential logic circuit out terminal and a clocked half-rail differential logic circuit out-not terminal.
The clocked half-rail differential logic circuit also includes a first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first transistor first flow electrode is coupled to a first supply voltage.
The clocked half-rail differential logic circuit also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first transistor second flow electrode is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked half-rail differential logic circuit out terminal.
The clocked half-rail differential logic circuit also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor second flow electrode is coupled to the third transistor first flow electrode and the third transistor second flow electrode is coupled to the clocked half-rail differential logic circuit out-not terminal.
The clocked half-rail differential logic circuit also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The second transistor control electrode is coupled to the fourth transistor first flow electrode and the clocked half-rail differential logic circuit out-not terminal. The third transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit out terminal.
The clocked half-rail differential logic circuit also includes a logic block, the logic block including a logic block first input terminal, a logic block second input terminal, a logic block out terminal, a logic block out-not terminal and a logic block fifth terminal. The logic block out terminal is coupled to the clocked half-rail differential logic circuit out terminal and the logic block out-not terminal is coupled to the clocked half-rail differential logic circuit out-not terminal.
The clocked half-rail differential logic circuit also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The fifth transistor first flow electrode is coupled to the logic block fifth terminal and the fifth transistor second flow electrode is coupled to a second supply voltage.
A clock signal is coupled to the fifth transistor control electrode of the fifth transistor of the clocked half-rail differential logic circuit. A clock-not signal is coupled to the first transistor control electrode of the first transistor of the clocked half-rail differential logic circuit and the fourth transistor control electrode of the fourth transistor of the clocked half-rail differential logic circuit.
As discussed in more detail below, the method and apparatus of the invention for creating clocked half-rail differential logic does not require the complex control circuitry of prior art half-rail differential logic circuits and is therefore simpler, saves space and is more reliable than prior art half-rail differential logic circuits. As a result, the clocked half-rail differential logic circuits of the invention are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.